//------------------------------------------------------------
//  Filename: vga_dma_top.v
//   
//  Author  : wlduan@gmail.com
//  Revise  : 2016-08-04 10:07
//  Description: 
//   
//  Copyright (C) 2014, YRBD, Inc. 					      
//  All Rights Reserved.                                       
//-------------------------------------------------------------
//

module vga_dma_ip # (
    parameter integer C_S00_AXI_DATA_WIDTH   = 32,
    parameter integer C_S00_AXI_ADDR_WIDTH   = 4,
    parameter integer C_M00_AXI_TARGET_SLAVE_BASE_ADDR = 32'h40000000,
    parameter integer C_M00_AXI_BURST_LEN    = 16,
    parameter integer C_M00_AXI_ID_WIDTH     = 1,
    parameter integer C_M00_AXI_ADDR_WIDTH   = 32,
    parameter integer C_M00_AXI_DATA_WIDTH   = 32,
    parameter integer C_M00_AXI_AWUSER_WIDTH = 0,
    parameter integer C_M00_AXI_ARUSER_WIDTH = 0,
    parameter integer C_M00_AXI_WUSER_WIDTH  = 0,
    parameter integer C_M00_AXI_RUSER_WIDTH  = 0,
    parameter integer C_M00_AXI_BUSER_WIDTH  = 0
)
(
    input  wire                                     s00_axi_aclk,
    input  wire                                     s00_axi_aresetn,
    input  wire [C_S00_AXI_ADDR_WIDTH-1 : 0       ] s00_axi_awaddr,
    input  wire [2 : 0                            ] s00_axi_awprot,
    input  wire                                     s00_axi_awvalid,
    output wire                                     s00_axi_awready,
    input  wire [C_S00_AXI_DATA_WIDTH-1 : 0       ] s00_axi_wdata,
    input  wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0   ] s00_axi_wstrb,
    input  wire                                     s00_axi_wvalid,
    output wire                                     s00_axi_wready,
    output wire [1 : 0                            ] s00_axi_bresp,
    output wire                                     s00_axi_bvalid,
    input  wire                                     s00_axi_bready,
    input  wire [C_S00_AXI_ADDR_WIDTH-1 : 0       ] s00_axi_araddr,
    input  wire [2 : 0                            ] s00_axi_arprot,
    input  wire                                     s00_axi_arvalid,
    output wire                                     s00_axi_arready,
    output wire [C_S00_AXI_DATA_WIDTH-1 : 0       ] s00_axi_rdata,
    output wire [1 : 0                            ] s00_axi_rresp,
    output wire                                     s00_axi_rvalid,
    input  wire                                     s00_axi_rready,

    input  wire                                     m00_axi_aclk,
    input  wire                                     m00_axi_aresetn,
    output wire [C_M00_AXI_ID_WIDTH-1 : 0         ] m00_axi_awid,
    output wire [C_M00_AXI_ADDR_WIDTH-1 : 0       ] m00_axi_awaddr,
    output wire [7 : 0                            ] m00_axi_awlen,
    output wire [2 : 0                            ] m00_axi_awsize,
    output wire [1 : 0                            ] m00_axi_awburst,
    output wire                                     m00_axi_awlock,
    output wire [3 : 0                            ] m00_axi_awcache,
    output wire [2 : 0                            ] m00_axi_awprot,
    output wire [3 : 0                            ] m00_axi_awqos,
    output wire [C_M00_AXI_AWUSER_WIDTH-1 : 0     ] m00_axi_awuser,
    output wire                                     m00_axi_awvalid,
    input  wire                                     m00_axi_awready,
    output wire [C_M00_AXI_DATA_WIDTH-1 : 0       ] m00_axi_wdata,
    output wire [C_M00_AXI_DATA_WIDTH/8-1 : 0     ] m00_axi_wstrb,
    output wire                                     m00_axi_wlast,
    output wire [C_M00_AXI_WUSER_WIDTH-1 : 0      ] m00_axi_wuser,
    output wire                                     m00_axi_wvalid,
    input  wire                                     m00_axi_wready,
    input  wire [C_M00_AXI_ID_WIDTH-1 : 0         ] m00_axi_bid,
    input  wire [1 : 0                            ] m00_axi_bresp,
    input  wire [C_M00_AXI_BUSER_WIDTH-1 : 0      ] m00_axi_buser,
    input  wire                                     m00_axi_bvalid,
    output wire                                     m00_axi_bready,
    output wire [C_M00_AXI_ID_WIDTH-1 : 0         ] m00_axi_arid,
    output wire [C_M00_AXI_ADDR_WIDTH-1 : 0       ] m00_axi_araddr,
    output wire [7 : 0                            ] m00_axi_arlen,
    output wire [2 : 0                            ] m00_axi_arsize,
    output wire [1 : 0                            ] m00_axi_arburst,
    output wire                                     m00_axi_arlock,
    output wire [3 : 0                            ] m00_axi_arcache,
    output wire [2 : 0                            ] m00_axi_arprot,
    output wire [3 : 0                            ] m00_axi_arqos,
    output wire [C_M00_AXI_ARUSER_WIDTH-1 : 0     ] m00_axi_aruser,
    output wire                                     m00_axi_arvalid,
    input  wire                                     m00_axi_arready,
    input  wire [C_M00_AXI_ID_WIDTH-1 : 0         ] m00_axi_rid,
    input  wire [C_M00_AXI_DATA_WIDTH-1 : 0       ] m00_axi_rdata,
    input  wire [1 : 0                            ] m00_axi_rresp,
    input  wire                                     m00_axi_rlast,
    input  wire [C_M00_AXI_RUSER_WIDTH-1 : 0      ] m00_axi_ruser,
    input  wire                                     m00_axi_rvalid,
    output wire                                     m00_axi_rready,

    input  wire                                     clk_vga,  
    output wire [4:0                              ] R,
    output wire [5:0                              ] G,
    output wire [4:0                              ] B,
            
    output wire                                     vga_h_sync,  
    output wire                                     vga_v_sync, 
    
    output wire                                     vga_pclk,
    output wire                                     vga_pwr_en,
    output wire                                     vga_de   
);
//--------------------------------------------------------
wire [31:0                         ] start_addr   ;
wire [31:0                         ] line_cnt     ;
wire [31:0                         ] row_cnt      ; 
wire                                 mm_read_start;
wire                                 mm_read_done ;  
//************** fifo interface **********************
wire                                 fifo_rd_clk  ;
wire                                 fifo_rd_en   ;
wire                                 fifo_empty   ;
wire [31:0                         ] fifo_dout    ;

//--------------------------------------------------------
wire rst  = ~s00_axi_aresetn;
wire vga_frm_sync = vga_v_sync;
wire data_err;
//--------------------------------------------------------
vga_dma_ip_v1_0_S00_AXI # (
    .C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
    .C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
) vga_dma_ip_v1_0_S00_AXI_inst (
    .S_AXI_ACLK    ( s00_axi_aclk    ) ,
    .S_AXI_ARESETN ( s00_axi_aresetn ) ,
    .S_AXI_AWADDR  ( s00_axi_awaddr  ) ,
    .S_AXI_AWPROT  ( s00_axi_awprot  ) ,
    .S_AXI_AWVALID ( s00_axi_awvalid ) ,
    .S_AXI_AWREADY ( s00_axi_awready ) ,
    .S_AXI_WDATA   ( s00_axi_wdata   ) ,
    .S_AXI_WSTRB   ( s00_axi_wstrb   ) ,
    .S_AXI_WVALID  ( s00_axi_wvalid  ) ,
    .S_AXI_WREADY  ( s00_axi_wready  ) ,
    .S_AXI_BRESP   ( s00_axi_bresp   ) ,
    .S_AXI_BVALID  ( s00_axi_bvalid  ) ,
    .S_AXI_BREADY  ( s00_axi_bready  ) ,
    .S_AXI_ARADDR  ( s00_axi_araddr  ) ,
    .S_AXI_ARPROT  ( s00_axi_arprot  ) ,
    .S_AXI_ARVALID ( s00_axi_arvalid ) ,
    .S_AXI_ARREADY ( s00_axi_arready ) ,
    .S_AXI_RDATA   ( s00_axi_rdata   ) ,
    .S_AXI_RRESP   ( s00_axi_rresp   ) ,
    .S_AXI_RVALID  ( s00_axi_rvalid  ) ,
    .S_AXI_RREADY  ( s00_axi_rready  ) ,

    .start_addr    ( start_addr      ) ,
    .line_cnt      ( line_cnt        ) ,
    .row_cnt       ( row_cnt         ) ,
    .vga_pwr_en    ( vga_pwr_en      ) ,
    .data_err      ( data_err        ) ,
    .mm_read_start ( mm_read_start   ) ,
    .mm_read_done  ( mm_read_done    ) 
);
//--------------------------------------------------------
vga_dma_ip_v1_0_vtg vga_dma_ip_v1_0_vtg_inst (
    .clk_vga        ( clk_vga          ) ,
    .rst            ( rst              ) ,       
    .R              ( R                ) ,
    .G              ( G                ) ,
    .B              ( B                ) ,
    
    .vga_pclk       ( vga_pclk         ) ,
    .vga_h_sync     ( vga_h_sync       ) ,
    .vga_v_sync     ( vga_v_sync       ) , 
    .vga_de         ( vga_de           ) ,
    
    .fifo_rd_clk    ( fifo_rd_clk      ) ,
    .fifo_rd_en     ( fifo_rd_en       ) ,
    .fifo_empty     ( fifo_empty       ) ,
    .fifo_dout      ( fifo_dout        ) ,
    
    .data_err       ( data_err         )
);
//--------------------------------------------------------
vga_dma_ip_v1_0_M00_AXI # (
    .C_M_TARGET_SLAVE_BASE_ADDR(C_M00_AXI_TARGET_SLAVE_BASE_ADDR),
    .C_M_AXI_BURST_LEN(C_M00_AXI_BURST_LEN),
    .C_M_AXI_ID_WIDTH(C_M00_AXI_ID_WIDTH),
    .C_M_AXI_ADDR_WIDTH(C_M00_AXI_ADDR_WIDTH),
    .C_M_AXI_DATA_WIDTH(C_M00_AXI_DATA_WIDTH),
    .C_M_AXI_AWUSER_WIDTH(C_M00_AXI_AWUSER_WIDTH),
    .C_M_AXI_ARUSER_WIDTH(C_M00_AXI_ARUSER_WIDTH),
    .C_M_AXI_WUSER_WIDTH(C_M00_AXI_WUSER_WIDTH),
    .C_M_AXI_RUSER_WIDTH(C_M00_AXI_RUSER_WIDTH),
    .C_M_AXI_BUSER_WIDTH(C_M00_AXI_BUSER_WIDTH)
) vga_dma_ip_v1_0_M00_AXI_inst (
    .M_AXI_ACLK    ( m00_axi_aclk         ) ,
    .M_AXI_ARESETN ( m00_axi_aresetn      ) ,
    .M_AXI_AWID    ( m00_axi_awid         ) ,
    .M_AXI_AWADDR  ( m00_axi_awaddr       ) ,
    .M_AXI_AWLEN   ( m00_axi_awlen        ) ,
    .M_AXI_AWSIZE  ( m00_axi_awsize       ) ,
    .M_AXI_AWBURST ( m00_axi_awburst      ) ,
    .M_AXI_AWLOCK  ( m00_axi_awlock       ) ,
    .M_AXI_AWCACHE ( m00_axi_awcache      ) ,
    .M_AXI_AWPROT  ( m00_axi_awprot       ) ,
    .M_AXI_AWQOS   ( m00_axi_awqos        ) ,
    .M_AXI_AWUSER  ( m00_axi_awuser       ) ,
    .M_AXI_AWVALID ( m00_axi_awvalid      ) ,
    .M_AXI_AWREADY ( m00_axi_awready      ) ,
    .M_AXI_WDATA   ( m00_axi_wdata        ) ,
    .M_AXI_WSTRB   ( m00_axi_wstrb        ) ,
    .M_AXI_WLAST   ( m00_axi_wlast        ) ,
    .M_AXI_WUSER   ( m00_axi_wuser        ) ,
    .M_AXI_WVALID  ( m00_axi_wvalid       ) ,
    .M_AXI_WREADY  ( m00_axi_wready       ) ,
    .M_AXI_BID     ( m00_axi_bid          ) ,
    .M_AXI_BRESP   ( m00_axi_bresp        ) ,
    .M_AXI_BUSER   ( m00_axi_buser        ) ,
    .M_AXI_BVALID  ( m00_axi_bvalid       ) ,
    .M_AXI_BREADY  ( m00_axi_bready       ) ,
    .M_AXI_ARID    ( m00_axi_arid         ) ,
    .M_AXI_ARADDR  ( m00_axi_araddr       ) ,
    .M_AXI_ARLEN   ( m00_axi_arlen        ) ,
    .M_AXI_ARSIZE  ( m00_axi_arsize       ) ,
    .M_AXI_ARBURST ( m00_axi_arburst      ) ,
    .M_AXI_ARLOCK  ( m00_axi_arlock       ) ,
    .M_AXI_ARCACHE ( m00_axi_arcache      ) ,
    .M_AXI_ARPROT  ( m00_axi_arprot       ) ,
    .M_AXI_ARQOS   ( m00_axi_arqos        ) ,
    .M_AXI_ARUSER  ( m00_axi_aruser       ) ,
    .M_AXI_ARVALID ( m00_axi_arvalid      ) ,
    .M_AXI_ARREADY ( m00_axi_arready      ) ,
    .M_AXI_RID     ( m00_axi_rid          ) ,
    .M_AXI_RDATA   ( m00_axi_rdata        ) ,
    .M_AXI_RRESP   ( m00_axi_rresp        ) ,
    .M_AXI_RLAST   ( m00_axi_rlast        ) ,
    .M_AXI_RUSER   ( m00_axi_ruser        ) ,
    .M_AXI_RVALID  ( m00_axi_rvalid       ) ,
    .M_AXI_RREADY  ( m00_axi_rready       ) ,
    //--------------------------------------------------------
    .start_addr    ( start_addr           ) ,
    .line_cnt      ( line_cnt             ) ,
    .row_cnt       ( row_cnt              ) ,
    .vga_frm_sync  ( vga_frm_sync         ) ,
    .mm_read_start ( mm_read_start        ) ,
    .mm_read_done  ( mm_read_done         ) ,
    //--------------------------------------------------------
    .fifo_rd_clk   ( fifo_rd_clk          ) ,
    .fifo_rd_en    ( fifo_rd_en           ) ,
    .fifo_empty    ( fifo_empty           ) ,
    .fifo_dout     ( fifo_dout            ) 
);

endmodule

